CIPSEC will be at IEEE HOST 2018

Monday, April 30, 2018
(Washington DC, USA)

CIPSEC will be at IEEE HOST 2018 (IEEE International Symposium on Hardware Oriented Security and Trust ) represented by University of Patras

IEEE International Symposium on Hardware Oriented Security and Trust (HOST) aims to facilitate the rapid growth of hardware-based security research and development. HOST highlights new results in the area of hardware and system security. Relevant research topics include techniques, tools, design/test methods, architectures, circuits, and applications of secure hardware.

Researches from UoP (A. P. Fournaris, A. Moschos, O. Koufopavlou) are authors of the paper "A Flexible Leakage Trace Collection Setup for Arbitrary Cryptographic IP Cores" accepted to be presented at this conference, one of most acclaimed, leading, IEEE conferences on Hardware Security.

Leakage Assessment and Side Channel Attacks (SCA) leakage trace acquisition tools and platforms require a considerable amount of time to collect millions of traces and rely on custom, hard to change or handle acquisition control mechanisms. To match these problems, in this paper, a flexible and scalable architecture for leakage trace collection is proposed, providing a fast, reconfigurable and flexible control mechanism that can be easily scaled to a wide variety of Devices under Test (DUT). The proposed system extends the two isolated chip approach that is adopted in several leakage trace collection boards by migrating all control, test vector generation and transmission, from off-board Personal Computer (PC) to an on board embedded system hardware based control mechanism. The proposed architecture using two isolated FPGA chips(a Control FPGA and a Cryptographic FPGA) introduces generic hardware interfaces (one for each FPGA) interconnected to a soft core microprocessor using a custom bus. Using this bus communication, the proposed architecture through the on-chip softcore processor software Application Program Interface (API) can fully control cryptographic components residing on a cryptographic FPGA regardless of the component's input - output number or bit-length thus providing high level of flexibility. The proposed architecture provides a toolset that can be used to structure various leakage assessment scenarios without changing the proposed control loop hardware structure. The proposed approach provides single, multiple encryption per control loop round and DUT clock frequency adjustment to enable accurate and fast leakage trace collection even for low-mid range oscilloscopes.