CIPSEC will be at DSD 2017

Date: 
Wednesday, August 30, 2017
Venue: 
(Vienna, Austria)

CIPSEC will be at DSD 2017 (Euromicro Conference on Digital System Design ) represented by University of Patras

The Euromicro Conference on Digital System Design (DSD) addresses all aspects of (embedded, pervasive and high-performance) digital and mixed HW/SW system engineering, covering the whole design trajectory from specification down to micro-architectures, digital circuits and VLSI implementations. It is a forum for researchers and engineers from academia and industry working on advanced investigations, developments and applications.

It focuses on today’s and future challenges of advanced embedded, high-performance and cyber-physical applications; system and processor architectures for embedded and high-performance HW/SW systems; design methodology and design automation for all design levels of embedded, high-performance and cyber-physical systems; modern implementation technologies from full custom in nanometer technology nodes, through FPGAs, to MPSoC infrastructures.

Researches from UoP (A. P. Fournaris, C. Dimopoulos and O. Koufopavlou) are authors of the paper "A Design Strategy for Digit Serial Multiplier based Binary Edwards Curve Scalar Multiplier Architectures" accepted to be presented at this conference.

Abstract:
Binary Edwards Curves (BEC) constitute an alternative to the standardized Weierstrass elliptic curve (EC) equations since the latter have intrinsic side channel attack vulnerabilities due to their lack of point operation uniformity. Thus, BECs have gained popularity over the past few years due to their uniformity, operation regularity, completeness and implementation attractiveness. However, BEC Scalar multiplication hardware implementations are still lacking in performance when compared to their Weierstrass equivalent. In this paper, a design strategy/methodology is proposed in order to realize BEC Scalar multipliers with a good trade-off between computation speed and utilized hardware resources. The strategy is based on a GF(2^k) operations arallelism mechanism that aims at the minimization of idle states in the utilized processing elements as well as the minimization of employed storage and control elements. A BEC SM architecture is proposed in order to describe the realization of the proposed strategy and its benefits are analyzed. In order to evaluate the efficiency of the proposed architecture an implementation was made in FPGA technology for GF(2^{233}) fields with BECs using d1 = d2. When compared to other works, the implementation expressed very balanced results.